In the integrated circuit industry, the performance of electrical devices can be improved by increasing the capacitance between a gate electrode and a channel region. The common method by which this capacitance can be increased is to decrease the thickness of the gate dielectric to below 100 angstroms. Currently, in the industry, the thickness of gate oxides are rapidly approaching 40 angstroms in thickness and below. At this thickness and below, the use of silicon dioxide as a gate dielectric is limited. Once silicon dioxide is formed to a thickness of less than 40 angstroms, direct tunneling may occur through the gate dielectric to the channel region, thereby increasing leakage current associated with the gate electrode and the channel region, causing an increase in power consumption.
Since reducing the thickness of the gate dielectric inherently increases gate-to-channel leakage current, alternative methods have been sought to reduce this leakage current while maintaining thin SiO.sub.2 equivalent thickness. One method investigated by the industry has been to use higher dielectric constant (high-k or high-.epsilon.) materials as the gate dielectric material whereby the increased permitivity (.epsilon.) of the material resultes in an increase in the gate-to-channel capacitance resulting in a higher performance electrical device. Note that the capacitance is C=.epsilon.A/t.sub.ox wherein a gate dielectric having a higher .epsilon. allows for the use of thicker gate dielectrics (i.e., t.sub.ox greater than 40 angstroms) whereby greater capacitance and device speed is achieved with less leakage current. However, the use of high-k dielectrics for gate dielectric materials is disadvantageous in integrated circuits (ICs) because high dielectric materials contain greater number of bulk traps and interface traps than gate dielectrics made from thermally grown SiO.sub.2. These traps adversely effect both subthreshold slope and threshold voltage (V.sub.t) operation of electric devices. Therefore, the integrated circuit industry is seeking solutions to enable fabrication of an ultra thin, high-reliability, high-k gate dielectric, to form faster devices while minimizing the trap disadvantages discussed above.
The industry has first sought to improve gate dielectric performance by curing plasma etch damage which occurs within the substrate after plasma etching of a polysilicon gate electrodes. When a polysilicon gate electrode is patterned/etched using a plasma etch environment, the energized plasma environment results in plasma damage to the substrate which is in close proximity to the gate electrode region. By using a dry oxygen (O.sub.2) reoxidation process, which oxidizes the damaged portion of the substrate and provides the necessary heat to heal the substrate damage, the plasma etch damage is removed from the transistor's active regions.
A dry reoxidation is preferred over wet reoxidation processing for this polysilicon reoxidation step for many reasons. First, wet oxidation has a different chemistry from dry oxidation whereby oxidation using wet techniques occurs at a rate which is faster than those using dry techniques. In other words, if a wet reoxidation process were used in the prior art, the polysilicon gate electrode would be consumed at a faster rate than if dry oxidation were used. The consumption of the polysilicon gate electrode will be further exacerbated if the doping concentration in the polysilicon gate is high. In addition, a higher oxidation rate will result in "bird's beaking" of the polysilicon gate electrode whereby the effective length (L.sub.EFF) of the resulting transistor device may be adversely altered.
In addition, because wet oxidation results in a thicker oxide being formed over the polysilicon region, lightly doped drain (LDD) source and drain formations for the transistor may be displaced too far from a gate electrode edge, resulting in higher on resistance (R.sub.on) for the transistor. Therefore, in summary, polysilicon reoxidation processing is performed using dry oxidation in the industry, and is not performed using a wet reoxidation environment.
The industry has attempted to use high-k dielectric materials or CVD silicon dielectrics to improve device speed and gate oxide integrity. A concern with the formation of high-k dielectrics and Chemical Vapor Deposition (CVD) silicon dioxide has been the formation of traps in the dielectric bulk and dielectric interface to the substrate. A proposed solution has been to limit the effects of these trap sites by annealing chemically vapor deposited (CVDed) dielectric materials in a wet environment. This process is taught by Sano, et al., in a paper entitled "High Quality SIO.sub.2 /SI Interfaces of Poly-crystalline Silicon Thin Film Transistors by Annealing In Wet Atmosphere", IEEE Electron Device Letters, Vol. 16, No. 5, May 1995. In this paper, Sano teaches that an SiO.sub.2 layer is chemical vapor deposited on a silicon-based material. This silicon dioxide (SiO.sub.2) film is then annealed at a very low non-oxidizing temperature of 270.degree. C. for a period of time to decrease the interface trap density between the silicon dioxide and the underlying silicon-based material This low temperature anneal, as taught by Sano, does nothing to correct plasma damage caused by the etching of the gate and dielectric material. Furthermore, Sano does not teach that the annealed SiO.sub.2 is the gate dielectric of a bulk transistor device. In addition, Sano teaches the use of conventional silicon dioxide (SiO.sub.2) which cannot progress below 40 angstroms in thickness without suffering high leakage current densities as discussed above. Therefore, Sano does not teach a method of forming a high dielectric constant gate dielectric having reduced trap sites and reduce substrate plasma damage.
In addition, the industry has attempted to create electrical devices having higher performance by utilizing higher dielectric materials, such as silicon nitride, as gate dielectrics. One such teaching is found by Wang, et al., in a paper entitled "Effects of Water Vapor Anneal on MIS Devices Made of Nitrided Gate Dielectrics", 1996 Symposium on VLSI Technology Digest of Technical Papers, 1996. Wang teaches two different embodiments. In a first embodiment, Wang teaches that silicon nitride is deposited to function as a gate dielectric. Directly after the silicon nitride deposition, a low temperature non-oxidizing annealing step is performed at 500.degree. C. on the nitride layer. This anneal, while reducing trap sites within the nitride layer, will not repair plasma damage or perform any type of advantageous reoxidation process. After this anneal process, a metal gate is then formed by Wang.
In a second embodiment, as taught by Wang, the silicon nitride layer is formed first. After the nitride layer is formed, an aluminum metal gate is formed over the nitride gate dielectric. The formation of the aluminum gate is then followed by a wet anneal process at a low temperature of 520.degree. C. It is not possible for Wang to perform an oxidation step to cure plasma damage, because of the fact that Wang has used a metal gate. At temperatures higher than 520.degree. C., the aluminum gates would be destroyed, degraded, severely oxidized, or the like all of which are highly disadvantageous. Therefore, the teachings of Wang do little to reduce plasma damage and cannot be modified to reduce substrate plasma damage due to thermal constraints.
Therefore, the need exists for an improved gate dielectric for a polysilicon-gated transistor. The improved gate dielectric region having a high dielectric constant, reduced trap sites, and reduced substrate plasma damage, whereby threshold voltage and subthreshold slope are not adversely effected while an increase in current drive (I.sub.ds) current is achieved. It would further be advantageous to integrate this process into current processes such that process complexity is not increased and thermal budget is not affected.